In normal microprocessor (computer) operations data is received from a peripheral device in a two step process. In the first step data is read from a peripheral device into a microprocessor register. The second step involves writing data from the register into a microprocessor memory location. Likewise two steps are required to transmit data from the microprocessor to the peripheral device. A read from memory into the register step and a write from the register to the peripheral device step.
The serial burst data transfer rate of peripheral equipment connected to a microprocessor (computer) often exceeds the rate at which the microprocessor executes a read and write instruction. In such a circumstance an external buffer is required to temporarily store the high speed burst data received from the peripheral equipment and feed the data at a lower speed to the connected microprocessor. Note, while the short term burst data rate of the peripheral equipment may exceed the microprocessor's read/write data rate it is obvious that the long term data rate of the peripheral equipment must, to prevent any loss of data, be less than the read-write data rate of the microprocessor. In the prior art a shift register having a length equal to the length of the data burst is used to buffer both the input and output of the microprocessor. In addition to the shift register, complex clocking, multiplexing and demultiplexing circuits are required to properly interface the microprocessor to the peripheral equipment. The circuit complexity is further compounded for peripheral devices which operates in a simultaneous transmit/receive bit synchronous manner requiring a bit to be transmitted for each bit received.
It is thus a problem to interface serial high speed bit synchronous burst data operated peripheral equipment with a microprocessor incapable of reading and writing at the serial burst data rate.